The CCITT recommendations G.707, G.708 and G.709 specify a synchronous digital hierarchy SDH, which enables the multiplexing of the signals of existing PCM systems, such as 2, 8, 34 and 140 Mbit/s, into a synchronous frame of 155 Mbit/s called STM-1 (synchronous transfer module). The structure of the STM-1 frame is illustrated in FIG. 1. The frame is usually shown as a unit comprising nine lines each having 270 bytes. The first nine bytes on each line contain a section overhead and AU pointer bytes. The remaining portion of the transfer frame STM-1 contains one or more administration units AU. In this specific case, there is an administration unit AU-4 of the highest level, in which a virtual container VC-4 similarly of the highest level is placed, and e.g. a 139264 kbit/s plesiochronous information signal can be mapped directly in the virtual container VC-4. Alternatively, the transfer frame STM-1 may contain several lower-level administration units AU in each one of which a corresponding virtual container VC of the lowest level is placed. In FIG. 1, the VC-4 comprises a 1-byte path overhead POH and a 240-byte information bit group at the start of both of which a special control byte is placed. Some of the control bytes are used, e.g. for performing interface justification in connection with mapping when the rate of the information signal to be mapped deviates to some extent from its nominal value. Mapping of the information signal into the transfer frame STM-1 is described, e.g. in the patent applications AU-B-34639/89 and FI-914746.
Each byte in the unit AU-4 has a position number. The above-mentioned AU pointer contains the position of the first byte of the container VC-4 in the unit AU-4. In addition, by means of the pointers, so-called positive or negative pointer justifications can be performed at the different locations of the SDH network. If a VC having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock frequency of the VC, the data buffer will be filled up. This requires negative justification: one byte is transferred from the received VC into the overhead section, while the pointer value is decreased by one.
If the rate of the received VC is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification in which a stuff byte is added to the VC and the pointer value is incremented by one.
Bit justification (interface justification) used in mapping as well as pointer justification cause phase jitter, which should be compensated for by the desynchronizer on leaving the SDH network. Phase jitter and its compensation are described, e.g. in Simulation Results and Field Trial Experience of Justification Jitter, Ralph Urbansky, 6th World Telecommunication Forum, Geneva, Oct. 10-15 1991, International Telecommunication Union, Part 2, Vol III, p. 45 to 49.
For this purpose, the prior art desynchronizers comprise a data buffer with an associated analog phase-locked loop (PLL) which phase-locks the read clock of the data buffer to the write clock. As the PLL operates in the same way as a lowpass filter, it removes jitter except for jitter components of the lowest frequency. For instance, the pointer justification of the SDH typically generates much more intensive jitter components than bit justification as individual phase discontinuities in the pointer justification are e.g. 8 or 24 frame intervals UI and as the frequency of occurrence of phase discontinuities induced by pointer justifications may represent a very low frequency difficult to filter in the PLL of the desynchronizer. Adequate suppression of pointer jitter by filtering would require that the bandwidth of the loop should be very low (the absolute value depends on the rate of the interface). FIGS. 2 and 3 show how the jitter peaks induced by two pointer justifications of 24 UI (measured from the output of the desynchronizer through a measuring filter specified by the CCITT) can be reduced to an acceptable maximum level of about 0.2 UI by drastic filtering when the bandwidth of the PLL at e.g. 140 Mbit/s is about 2 Hz. However, no pointer justifications are needed in normal operation, and only bit justifications are active. Accordingly, the dimensioning of the phase-locked loop of the desynchronizer on the basis of pointer justifications is unreasonable as the bandwidth of the PLL could be even ten times higher from the viewpoint of bit justification. The locking of the PLL would thereby also be more reliable and the locking time would be substantially shorter.
One prior art solution to the problem is bit leaking, in which pointer induced phase discontinuities are removed by a non-linear process (in the time domain), whereby incoming data bits are processed by a separate serial buffer so that the phase of the write clock and data applied to the buffer of the desynchronizer is advanced (or retarded) periodically, and so a stepwise phase shift is converted into a linear phase shift taking place over a longer period of time. The pointer justifications are thereby processed separately by a bit leaking buffer so that the bandwidth of the phase-locked loop of the desynchronizer itself can be increased so as to meet the requirements of the bit justifications. A problem with bit leaking is the bit-level serial data processing and the relatively complicated logic. It is further to be noted that it is not adequate that one pointer at a time can be processed but, in the worst case, the logic should be able to operate with tens of overlapping pointer justifications at different decay stages. Therefore, the use of this technique in a high-rate 140 Mbit/s desynchronizer is not advisable due to the increased power consumption, for instance.